In modern integrated circuits, devices such as transistors formed in a semiconductor substrate are interconnected by wires formed in interlevel dielectric (ILD) layers into circuits. At high current densities, the metal in the wires can migrate in the direction of electron flow building up at the anode end of the wire to the point where the buildup of metal causes delamination of the interlevel dielectric layers and extrusion of metal from the end of the wire. These extrusions can short to adjacent wires causing circuit failures. The remedy is to make wires wider and/or thicker to reduce current density, however wider lines use more integrated circuit chip real estate and makes dense wiring schemes more difficult if not impossible. The data gathered from extrusion monitors enables the use of wires of minimum wire cross-sectional areas in the integrated circuit.
Currently, the industry uses electromigration or extrusion test structures to monitor this failure mechanism. However, current monitors only can detect fails, which extend laterally to adjacent wires in the same ILD layer. However, extrusions that extend vertically and short to wires in upper or lower ILD layers are not detected. Therefore, there is a need for an extrusion monitor that can detect vertical as well as lateral extrusions.